A test bench based on field-programmable gate arrays (FPGAs) has been developed to reduce the cost of testing nonvolatile memory circuits. Specifications for endurance testing of memories can require test times as long as weeks — often impractically long in the case of commercial memory testers, which are expensive. The present FPGA-based test bench not only costs less than commercial memory testers do but can also be configured with multiple FPGAs to enable the simultaneous testing of many more memory chips than can be tested simultaneously on a commercial memory tester.
In comparison with the design of a commercial memory tester, the design of this test bench is more application specific: The test bench is designed to perform certain reliability and endurance (life-cycle) tests on certain ferro- electric random-access memory (FRAM) and electrically erasable, programmable read-only memory (EEPROM) chips. The application-specific nature of the design offers advantages of lower cost, less complexity, and greater suitability for endurance testing. There is one disadvantage: Whereas a commercial memory tester can perform tests on many different types of memory chips without recoding, the FPGA-based test bench must be recoded for different kinds of chips.
The test bench was developed by use of a commercial prototyping board and a commercial 10,000-gate FPGA. At present, the test bench can be configured to operate as either of two testers. The first tester performs a reliability test that detects address-decoder faults and stuck-at faults and that cycles through all of the addresses in a memory. The second tester performs an endurance test, in which it writes to, and reads back from, the same address repeatedly. The second tester can perform endurance tests faster than can a commercial memory tester, especially in cases of memory circuits that are slow by modern standards.
When an error is detected in a test, the data logged includes the error number, the address where the error occurred, the cycle number (where one cycle is defined as one read-and-write operation to a single address), the incorrect data value read, and (in the case of the reliability test) the portion of the test in which the error occurred. The error data can be logged by one of two methods. In the first method, which is applicable if the tester is connected to the parallel port of a personal computer, a small program written for this purpose sends the data to the computer screen and saves the data in a file. The second method, which is still undergoing development, would enable the tester to be totally independent of a personal computer. In this second method, the FPGA bit stream would be written into an EEPROM, which would be used to configure the FPGA on power-up. Instead of using a personal computer to log the error data, a light-emitting-diode display would be used to read out the error data when a switch was flipped. The display would also indicate whether testing was taking place, and whether an error had occurred.
This work was done by Jagdishbhai Patel, Jeffrey Namkung, and Vikram Rao of Caltech for NASA’s Jet Propulsion Laboratory.
This Brief includes a Technical Support Package (TSP).
FPGA-Based Test Bench for Nonvolatile Electronic Memories
(reference NPO-30374) is currently available for download from the TSP library.
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Overview
The document discusses the development of an FPGA-based test bench for testing non-volatile electronic memories, specifically targeting FRAM (ferroelectric random-access memory) and EEPROM (electrically erasable programmable read-only memory) chips. Created by Jagdishbhai Patel, Jeffrey Namkung, and Vikram Rao at NASA's Jet Propulsion Laboratory, this innovative solution addresses the high costs and impractical long test times associated with commercial memory testers.
The test bench utilizes a XILINX XC4010E FPGA, which has 10,000 gates, to perform two primary types of tests: reliability testing and endurance testing. The reliability test, known as the MATS+ memory test, detects address-decoder faults and stuck-at faults while cycling through all memory addresses. The endurance test involves repeatedly writing to and reading from the same memory address, allowing for faster testing, especially for slower memory technologies.
One of the key advantages of this FPGA-based test bench is its ability to test multiple chips simultaneously at a lower cost compared to commercial testers. The design is application-specific, tailored to perform specific reliability and endurance tests, which enhances its efficiency and suitability for endurance testing. However, this specificity also means that the test bench must be reprogrammed for different types of memory chips, unlike commercial testers that can handle various memory types without recoding.
Error logging is an essential feature of the test bench. When an error is detected, the system logs critical data, including the error number, the address of the error, the cycle number, the incorrect data value read, and the specific portion of the test during which the error occurred. There are two methods for logging this error data: one involves connecting the tester to a personal computer's parallel port, where a program outputs the data to the screen and saves it to a file. The second method, still under development, aims to make the tester independent of a PC by using an EEPROM to configure the FPGA on power-up and an LED display for error data readout.
Overall, this FPGA-based test bench represents a significant advancement in the testing of non-volatile memories, offering a cost-effective, efficient, and specialized solution for reliability and endurance testing.
