All efforts to develop electronic equipment reach a stage where they need a board test station for each board. The SMAP digital system consists of three board types that interact with each other using interfaces with critical timing. Each board needs to be tested individually before combining into the integrated digital electronics system. Each board needs critical timing signals from the others to be able to operate. A bench test system was developed to support test of each board. The test system produces all the outputs of the control and timing unit, and is delivered much earlier than the timing unit.
Timing signals are treated as data. A large file is generated containing the state of every timing signal at any instant. This file is streamed out to an IO card, which is wired directly to the device-under-test (DUT) input pins. This provides a flexible test environment that can be adapted to any of the boards required to test in a standalone configuration. The problem of generating the critical timing signals is then transferred from a hardware problem to a software problem where it is more easily dealt with.
The first board to be tested was the ADC Digital Processor board (ADP). The ADP needed a complex Xilinx configuration data stream to operate, plus timing signals. The IO card is wired directly to the configuration and timing inputs of the board through VME connectors. A slower pattern maker program combines the Xilinx configuration and desired timing into a large data file. This data file is clocked out at 40 MHz (32 bits of data) into 28 inputs of the ADP to make it run.
The formatter board needs data from an ADP, plus timing information from the control and timing unit. Data captured from the ADP in its standalone test is combined with timing information into a large file. The large file streams out the IO card and is wired to formatter inputs. Since the formatter has more inputs than the IO card has bits, several signals were crossstrapped (duplicated), making it appear to the formatter that it was receiving two ADP boards when it was in fact receiving two copies of the same ADP board. In combined ADP/formatter integration, the IO card emulates the timing unit only.
Using IO cards to emulate missing hardware for bench test is an older technology. The improvement here is the ability to stream out fresh data continuously for many tens of seconds with no gaps at 40 MHz. This allows precise control over timing with time tag information that varies over a wide range. This allows a much better bench test than would have been possible in short pulses.
By allowing more complete testing of the individual boards when they are ready rather than deferring test to integration, the delivery of the SMAP digital system is accelerated.
This work was done by Andrew C. Berkun and Anhua J. Chu of Caltech for NASA’s Jet Propulsion Laboratory.
The software used in this innovation is available for commercial licensing. Please contact Daniel Broderick of the California Institute of Technology at
This Brief includes a Technical Support Package (TSP).
Pattern Generator for Bench Test of Digital Boards
(reference NPO-48231) is currently available for download from the TSP library.
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Overview
The document outlines the development and implementation of a bench test system for digital boards used in NASA's Soil Moisture Active and Passive (SMAP) project, conducted at the Jet Propulsion Laboratory (JPL). The SMAP digital system comprises three types of boards that interact through critical timing interfaces, necessitating individual testing before integration into the overall system.
To facilitate this testing, a pattern generator was created to produce the necessary outputs from the Control and Timing unit, which is essential for the operation of each board. This test system generates timing control signals, serial data, and Xilinx configuration data, allowing for a flexible and adaptable testing environment. The methodology shifts the challenge of generating critical timing signals from hardware to software, making it easier to manage.
The testing process involves creating a large data file that captures the state of every timing signal at any given moment. This file is streamed to an Input/Output (IO) card, which connects directly to the input pins of the Device Under Test (DUT). The system operates at a clock speed of 40 MHz, enabling continuous data streaming for extended periods without gaps, which is crucial for accurate timing and unique data tagging.
The document emphasizes the advantages of this approach, including the ability to conduct thorough tests on individual boards as they become ready, rather than waiting for full system integration. This strategy accelerates the delivery schedule of the SMAP instrument by allowing for earlier identification and resolution of potential issues.
Additionally, the use of off-the-shelf hardware to generate the required signals enhances the efficiency of the bench test system. The document acknowledges the research's sponsorship by NASA and highlights the potential for this testing methodology to be applied to various types of complex digital boards beyond the SMAP project.
In summary, the Technical Support Package provides a comprehensive overview of the pattern generator's role in bench testing digital boards, showcasing its significance in ensuring the reliability and functionality of critical aerospace systems. The innovative approach not only streamlines the testing process but also contributes to the overall success of NASA's missions.
