Two improved schemes for the design and operation of photodiode-based CMOS (complementary metal oxide/ semiconductor) active-pixel sensors (APSs) afford zero image lag, low noise, and high linearity of response even under low illumination. Figure 1 schematically depicts the circuitry for one pixel according to a typical older scheme. In soft reset, the sensing node does not charge up to the power-supply potential (VDD), and depends strongly on the potential at the beginning of the reset. In hard reset, the sensing node charges up to a known potential, usually VDD.
For reasons that are complex and must therefore be omitted from this article for the sake of brevity, typical older soft- and hard-reset schemes entail disadvantages and advantages as follows:
- Soft reset advantageously results in low-noise output and a high power-supply rejection ratio (PSRR). However, disadvantageously, soft reset results in image lag of as much as 70 percent of the mean signal in the previous frame, and a markedly nonlinear response under low illumination.
- Hard reset advantageously eliminates image lag but disadvantageously results in increased read noise, dark current, and reduced power-supply ratio.
Under the improved schemes, the disadvantages are eliminated by resetting pixels first by hard reset and then by soft reset. Hard reset erases the memory from the previous frame, eliminating image lag and nonlinearity, while soft reset allows operation with low-read noise. Thus, low noise, zero image lag, and high linearity are achieved simultaneously.
Figure 2 illustrates the pixel circuits that are used for implementation of the two new schemes, which are characterized by the terms "flushed photodiode" and "hard-to-soft (HTS) reset photodiode," respectively. In the flushed-photodiode APS, the pixel circuit contains an additional line (denoted "HTSffÄBlack") for a row-decoded signal that controls the potential at the drain of the reset MOSFET (metal oxide/semiconductor field-effect transistor). Pulsing HTS reduces the drain potential, allowing the pixel to be reset in hard reset mode. In the HTS APS, no change in the pixel design is necessary. In this scheme, VDDis routed to each column through an n- and a p-channel MOSFET. The gate of the p-channel MOSFET is connected to a line (denoted "HTS") that carries a column-decoded signal. Pulsing HTS momentarily high during the reset phase causes the source of the reset MOSFET to reduce below VDD, causing the pixel to go into hard reset. The hard-reset level is determined by the size of the n-channel MOSFET, and is set to approximately VDD/2. In both schemes, soft reset of the pixel following the hard reset is achieved once the HTS pulse goes low.
This work was done by Bedabrata Pain, Guang Yang, Thomas Cunningham, and Bruce Hancock of Caltech for NASA's Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to
Technology Reporting Office
JPL
Mail Stop 122-116
4800 Oak Grove Drive
Pasadena, CA 91109
(818) 354-2240
Refer to NPO-20716
This Brief includes a Technical Support Package (TSP).
Photodiode-Based CMOS APSs with Zero-lag, Low-noise, High-linearity Design
(reference NPO20716) is currently available for download from the TSP library.
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Overview
The document is a NASA Technical Support Package detailing advancements in photodiode-based CMOS Active-Pixel Sensors (APSs) designed to enhance imaging technology. The primary focus is on two innovative schemes that address common issues in conventional imaging systems, such as image lag, noise, and linearity of response, particularly under low-light conditions.
Key features of the new technology include:
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Zero Image Lag: Unlike traditional imagers that can experience significant image lag (up to 10 milliseconds), the new design achieves zero image lag. This is crucial for applications requiring immediate image capture without delay.
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High Linearity: The sensors maintain high linearity even in low-light environments, eliminating dead zones and providing over 40 dB enhancement in low-light response. This improvement is vital for applications in various commercial imaging fields where accurate color and brightness representation is essential.
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Low Noise: The new APSs exhibit noise levels that are less than half of those found in conventional devices utilizing hard-reset techniques. This reduction in noise enhances image clarity and detail, particularly in challenging lighting conditions.
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High Power Supply Rejection Ratio (PSRR): The design boasts a PSRR that is 40 dB higher than that of hard-reset systems without the need for a bypass capacitor. This feature minimizes the impact of power supply fluctuations on the sensor's performance, ensuring more stable and reliable imaging.
The document also discusses the operational principles behind the soft-reset technique, which allows for lower noise levels due to an inherent feedback mechanism. This method involves resetting the sensor using sub-threshold MOSFET current, which is less disruptive than traditional reset methods.
In addition to the technical specifications, the document emphasizes the potential applications of this technology across various sectors, including government and commercial imaging. The advancements in photodiode-based CMOS APSs are positioned to significantly improve the quality and efficiency of imaging systems, making them suitable for a wide range of uses.
Overall, the document presents a comprehensive overview of the novel photodiode-based CMOS imager technology, highlighting its improvements over prior art and its implications for future imaging applications.
