Active-Pixel-Sensor ICs With Photosites in Substrates

NASA's Jet Propulsion Laboratory, Pasadena, California

Focal-plane arrays of active-pixel sensors (photodetectors integrated with in-pixel readout transistors) would be designed and fabricated within the emerging technological discipline of silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated circuits (ICs), according to a proposal. SOI CMOS seems destined to supplant the more familiar bulk CMOS as the standard for fabrication of very-large-scale integrated (VLSI) circuits, during the next few years. Heretofore, it has been generally considered that functional APS circuits cannot be implemented in SOI CMOS because the layers of silicon for fabricating electronic devices on SOI wafers are so thin that optical absorbing volumes cannot be made large enough. In the proposed approach, photodetectors would be implemented within SOI silicon substrates in such a way as to obtain the desired functionality. Little or no departure from established SOI CMOS processing would be necessary. One disadvantage of SOI might be a tendency toward the floating-body effect, but it is possible to counteract this effect through appropriate design.

These Cross Sections (not to scale) represent unit cells of two of several APS designs proposed to be implemented in SOI CMOS.

The figure depicts two of several proposed APS designs. The unique features of these designs and the advantages of implementing them in SOI CMOS rather than bulk CMOS include the following:

The photodiode or photogate would incorporate part of the high-resistivity silicon substrate. This would impart a highly planar character to the device structure; the planar character would, in turn, prevent field-assisted increase in dark current (including dark current attributable to ionizing radiation).
The high resistivity of the substrate would make for a large depletion width, with consequent high quantum efficiency and thus high optical collection efficiency.
Because the size of the photosite would be much larger than the minimum under design rules, the photosite could be fabricated along with other substructures by standard SOI fabrication techniques.
The capacitance of the sensing node would be lower because the substrate capacitance would be lower. Lower sensing-node capacitance would translate to higher conversion gain and lower noise, and thus the ability to detect light at lower levels.
Complementary transistors would be placed in each pixel to obtain high dynamic range. A metal oxide semiconductor field-effect-transistor with p doping (p-MOSFET) would be incorporated for use as a reset gate that would enable reset all the way to the power-supply voltage (VDD). It is not possible to incorporate such a structure into an APS in bulk CMOS without adversely affecting the pixel size and increasing the potential for latch-up, but it is possible in SOI CMOS because SOI transistors are formed in isolated islands.
Cross-talk would be reduced because parasitic capacitances would be lower and because of the isolation of individual transistors.
In the absence of substrate coupling, timing patterns could be changed to enable the simultaneous operation of analog and digital subcircuits. The change in timing patterns would enable operation at higher speeds.
Photodetectors, in-pixel circuitry, and peripheral circuitry would all exhibit greater radiation hardness because silicon layers would be thinner and because of the prevention of field-assisted increase in dark current mentioned above. Furthermore, the isolation of transistors would afford immunity to latch-up.

This work was done by Bedabrata Pain of Caltech for NASA's Jet Propulsion Laboratory. NPO-20534