An integrated circuit (IC) physical layout has been developed for the HCD ASIC - an application-specific integrated circuit that decodes digital command signals transmitted from a ground station to a spacecraft (uplink commands). The HCD ASIC is described in "Hardware-Command-Decoding ASIC" (NPO-19615), which appears elsewhere in this issue of NASA Tech Briefs. The present physical layout will be converted to a mask for IC fabrication of the HCD ASIC.
The physical layout has been extensively simulated for its functions of receiving and decoding the uplink commands through a programmable read-only memory (PROM) interface, including conversion of the command data from the serial uplink format to parallel format. At the same time, the HCD ASIC provides detection of some triple bit errors, detection of all double bit errors, and correction of all single-bit errors in the uplink commands, plus detection of hardware faults, all at unprecedented speed. Another unique feature is the use of the double-buffer method for read/write and status for resolving overruns.
This work was done by Gary S. Bolotin, James A. Donaldson, Huy H. Luong, and Steven H. Wood of Caltech for NASA's Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to
Technology Reporting Office
JPL
Mail Stop 122-116
4800 Oak Grove Drive
Pasadena, CA 91109
(818) 354-2240
Refer to NPO-19628
This Brief includes a Technical Support Package (TSP).
ASIC physical layout for the HCD ASIC
(reference NPO19628) is currently available for download from the TSP library.
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Overview
The document presents a technical support package for the Hardware Command Decoder (HCD) application-specific integrated circuit (ASIC), developed for NASA's Jet Propulsion Laboratory (JPL). The HCD ASIC is designed to decode digital command signals transmitted from ground stations to spacecraft, facilitating efficient communication and control.
The physical layout of the HCD ASIC has undergone extensive simulation to ensure its functionality in receiving and decoding uplink commands. It utilizes a programmable read-only memory (PROM) interface to convert command data from a serial format to a parallel format. This design incorporates advanced error detection and correction capabilities, including the ability to detect triple bit errors, all double bit errors, and correct single-bit errors, thereby enhancing the reliability of command transmission.
A notable feature of the HCD ASIC is its implementation of a double-buffer method for read/write operations and status management, which effectively resolves data overruns. This innovative approach allows for unprecedented speed in processing commands, making it a significant advancement in spacecraft communication technology.
The document also outlines the Fault Detection Unit (FDU) associated with the HCD ASIC, which includes a self-test function that must be continuously passed for the system to remain healthy, online, and operational. The self-test sequence involves writing to three specific registers in a defined order, ensuring the integrity of the system.
The HCD/CRC chip integrates various functionalities, including the logic for the HCD, Critical Controller (CRC), ISB Interface, address decoder, and Fault Detection Unit, all of which are crucial for the effective operation of spacecraft systems. The document includes a block diagram illustrating the top-level architecture of the chip, highlighting its components and their interconnections.
The development of the HCD ASIC is credited to a team of inventors from Caltech, including Gary S. Bolotin, James A. Donaldson, Huy H. Luong, and Steven H. Wood. The document emphasizes that the contractor retains title to the invention, and inquiries regarding commercial use should be directed to the appropriate contact at Caltech.
Overall, this document serves as a comprehensive overview of the HCD ASIC's design, functionality, and significance in advancing spacecraft command and control systems, showcasing the innovative efforts of NASA and its partners in aerospace technology.
