A field-programmable gate array (FPGA) on a single lightweight, low power integrated-circuit chip has been developed to implement an azimuth pre-filter (AzPF) for a synthetic-aperture radar (SAR) system. The AzPF is needed to enable more efficient use of data-transmission and data-processing resources: In broad terms, the AzPF reduces the volume of SAR data by effectively reducing the azimuth resolution, without loss of range resolution, during times when end users are willing to accept lower azimuth resolution as the price of rapid access to SAR imagery. The data-reduction factor is selectable at a decimation factor, M, of 2, 4, 8, 16, or 32 so that users can trade resolution against processing and transmission delays.

In principle, azimuth filtering could be performed in the frequency domain by use of fast-Fourier-transform processors. However, in the AzPF, azimuth filtering is performed in the time domain by use of finite-impulse-response filters. The reason for choosing the time-domain approach over the frequency-domain approach is that the time-domain approach demands less memory and a lower memory-access rate.

The Prototype Circuit Board measures 6 by 10 in. (15.2 by 25.4 cm). The AzPF integrated circuit mounted on the board measures only about 2.5 in. (≈6.4 cm) square and consumes a power The AzPF operates on the raw digitized SAR data. The AzPF includes a digital in-phase/quadrature (I/Q) demodulator. In general, an I/Q demodulator effects a complex down-conversion of its input signal followed by low-pass filtering, which eliminates undesired sidebands. In the AzPF case, the I/Q demodulator takes offset video range echo data to the complex baseband domain, ensuring preservation of signal phase through the azimuth pre-filtering process. In general, in an SAR I/Q demodulator, the intermediate frequency (fI) is chosen to be a quarter of the range-sampling frequency and the pulse repetition frequency (fPR) is chosen to be a multiple of fI.

The AzPF also includes a polyphase spatial-domain pre-filter comprising four weighted integrate-and-dump filters with programmable decimation factors and overlapping phases. To prevent aliasing of signals, the bandwidth of the AzPF is made 80 percent of fPR/M. The choice of four as the number of overlapping phases is justified by prior research in which it was shown that a filter of length 4M can effect an acceptable transfer function. The figure depicts prototype hardware comprising the AzPF and ancillary electronic circuits. The hardware was found to satisfy performance requirements in real-time tests at a sampling rate of 100 MHz.

This work was done by Mimi Gudim, Tsan-Huei Cheng, Soren Madsen, Robert Johnson, Charles T-C Le, Mahta Moghaddam, and Miguel Marina of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Semiconductors & ICs category.

NPO-30741

Topics:
Electronic equipment Hardware Logistics Parts Powertrains Radar Research and development Semiconductors Semiconductors & ICs Transmissions
This Brief includes a Technical Support Package (TSP).
Document cover
Single-Chip FPGA Azimuth Pre-Filter for SAR

(reference NPO-30741) is currently available for download from the TSP library.

Don't have an account?

Magazine cover
NASA Tech Briefs Magazine

This article first appeared in the May, 2005 issue of NASA Tech Briefs Magazine (Vol. 29 No. 5).

Read more articles from the archives here.

Overview

The document is a Technical Support Package from NASA's Jet Propulsion Laboratory detailing the Single-Chip FPGA Azimuth Pre-Filter (AzPF) designed for Synthetic Aperture Radar (SAR) applications. The AzPF aims to enhance data processing efficiency for spaceborne SAR systems, particularly in scenarios where large area mappings are required, such as monitoring dynamic events like floods, fires, and earthquakes.

The research emphasizes the need for efficient data handling in SAR missions, where high-resolution data is often necessary but can lead to significant downlink bandwidth requirements. For instance, a typical spaceborne SAR has an azimuth resolution of 6 meters and a downlink data rate of approximately 105 Mbps. The AzPF allows for a reduction in required downlink bandwidth by a decimation factor (M), which corresponds to a proportional degradation in azimuth resolution. This trade-off is particularly beneficial for missions that do not require high resolution in all data acquisition scenarios.

The document outlines the major steps involved in SAR processing, including azimuth compression, corner turning, range compression, and multi-looking. It also presents various performance metrics and design considerations for the AzPF, including the use of different windowing techniques and algorithms to optimize filter performance.

Figures included in the document illustrate the performance of the AzPF in terms of Peak Signal-to-Noise Ratio (PSLR), Integrated Signal-to-Noise Ratio (ISLR), Mean Logarithmic Error (MLW), and 3dBW across different quantization bits and decimation ratios. These visual representations help convey the effectiveness of the AzPF in reducing data rates while maintaining acceptable levels of signal quality.

Overall, the document serves as a comprehensive overview of the AzPF's design, performance evaluation, and implementation challenges, highlighting its potential to significantly improve the efficiency of SAR data processing and transmission. The advancements presented are expected to have broader technological, scientific, and commercial applications, contributing to the future of aerospace technology and remote sensing capabilities.