Single-slope analog-to-digital converters (ADCs) are particularly useful for on-chip digitization in focal plane arrays (FPAs) because of their inherent monotonicity, relative simplicity, and efficiency for column-parallel applications, but they are comparatively slow. Square-root encoding can allow the number of code values to be reduced without loss of signal- to-noise ratio (SNR) by keeping the quantization noise just below the signal shot noise. This encoding can be implemented directly by using a quadratic ramp. The reduction in the number of code values can substantially increase the quantization speed. However, in an FPA, the fixed pattern noise (FPN) limits the use of small quantization steps at low signal levels. If the zero-point is adjusted so that the lowest column is onscale, the other columns, including those at the center of the distribution, will be pushed up the ramp where the quantization noise is higher.
Additionally, the finite frequency response of the ramp buffer amplifier and the comparator distort the shape of the ramp, so that the effective ramp value at the time the comparator trips differs from the intended value, resulting in errors. Allowing increased settling time decreases the quantization speed, while increasing the bandwidth increases the noise.
The FPN problem is solved by breaking the ramp into two portions, with some fraction of the available code values allocated to a linear ramp and the remainder to a quadratic ramp. To avoid large transients, both the value and the slope of the linear and quadratic portions should be equal where they join. The span of the linear portion must cover the minimum offset, but not necessarily the maximum, since the fraction of the pixels above the upper limit will still be correctly quantized, albeit with increased quantization noise. The required linear span, maximum signal and ratio of quantization noise to shot noise at high signal, along with the continuity requirement, determines the number of code values that must be allocated to each portion.
The distortion problem is solved by using a lookup table to convert captured code values back to signal levels. The values in this table will be similar to the intended ramp value, but with a correction for the finite bandwidth effects.
Continuous-time comparators are used, and their bandwidth is set below the step rate, which smoothes the ramp and reduces the noise. No settling time is needed, as would be the case for clocked comparators, but the low bandwidth enhances the distortion of the non-linear portion. This is corrected by use of a return lookup table, which differs from the one used to generate the ramp. The return lookup table is obtained by calibrating against a stepped precision DC reference. This results in a residual non-linearity well below the quantization noise. This method can also compensate for differential non-linearity (DNL) in the DAC used to generate the ramp.
The use of a ramp with a combination of linear and quadratic portions for a single-slope ADC is novel. The number of steps is minimized by keeping the step size just below the photon shot noise. This in turn maximizes the speed of the conversion. High resolution is maintained by keeping small quantization steps at low signals, and noise is minimized by allowing the lowest analog bandwidth, all without increasing the quantization noise. A calibrated return lookup table allows the system to maintain excellent linearity.
This work was done by Chris J. Wrigley, Bruce R. Hancock, Kenneth W. Newton, and Thomas J. Cunningham of Caltech for NASA’s Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
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NPO-47836
This Brief includes a Technical Support Package (TSP).
Mixed Linear/Square-Root Encoded Single-Slope Ramp Provides Low-Noise ADC With High Linearity for Focal Plane Arrays
(reference NPO-47836) is currently available for download from the TSP library.
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Overview
The document is a Technical Support Package from NASA's Jet Propulsion Laboratory (JPL) detailing advancements in Analog-to-Digital Converter (ADC) technology, specifically focusing on a Mixed Linear/Square-Root Encoded Single-Slope Ramp design. This innovation aims to improve the performance of ADCs used in focal plane arrays, which are critical in various applications, including imaging and sensing technologies.
The key feature of this ADC design is its ability to provide low noise and high linearity, which are essential for accurately converting analog signals into digital form. The document discusses the challenges associated with speed-resolution limitations in ADCs, particularly due to photon shot noise. Shot noise arises from the statistical nature of photon arrivals, which follow a Poisson distribution. At high signal levels, shot noise can dominate, limiting the effectiveness of fine quantization steps. Conversely, at low signal levels, where shot noise is minimal, finer quantization can enhance resolution.
To address these challenges, the document introduces a method of varying the size of quantization steps based on the signal level. This approach allows for a more efficient allocation of quantization resources, shifting steps from high signal levels—where they are less useful—to lower levels, where they can significantly improve performance. The quantization noise variance is mathematically expressed, highlighting the relationship between signal charge and code value.
The document also emphasizes the implementation of square root encoding, which allows for a more effective representation of signal values. By using a quadratic ramp instead of a linear one, the design can quantize signals ranging from 0 to 50,000 electrons with only 256 code values, resulting in a minimal degradation of the signal-to-noise ratio.
Overall, this Technical Support Package serves as a comprehensive overview of the advancements in ADC technology at JPL, showcasing the potential for improved performance in various applications. It underscores the importance of innovative approaches in addressing the inherent challenges of signal processing in aerospace and other fields. The document is part of NASA's efforts to disseminate aerospace-related developments with broader technological, scientific, and commercial implications.
