A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field-programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse- FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board.

The Board Saver is shown here in a simplified plan view (greatly reduced number of via holes) and not to scale, to facilitate understanding of its basic layout.
The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes — one for each contact pad — along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later.

The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

This work was done by Andrew Berkun of Caltech for NASA’s Jet Propulsion Laboratory. NPO-44745

Topics:
Cutting Inspections Joining Manufacturing processes Materials properties Semiconductors & ICs Wear
This Brief includes a Technical Support Package (TSP).
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Board Saver for Use With Developmental FPGAs

(reference NPO-44745) is currently available for download from the TSP library.

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NASA Tech Briefs Magazine

This article first appeared in the September, 2009 issue of NASA Tech Briefs Magazine (Vol. 33 No. 9).

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Overview

The document outlines NASA's innovative solution known as the "Board Saver for Use With Developmental FPGAs," identified by the technical reference NPO-44745. Developed at NASA's Jet Propulsion Laboratory (JPL), this technology addresses a common challenge in FPGA design iterations, which often require the replacement of soldered components on flight boards. Frequent changes can lead to wear and damage to the board, making it difficult to maintain its functionality over time.

The Board Saver is a specialized printed circuit board (PCB) designed to be temporarily mounted to the flight board without requiring additional clearance above or to the side. It features a footprint compatible with the CQ172 FPGA, allowing a non-flight FPGA to be soldered and removed multiple times from the top of the Board Saver. This design eliminates the need for lead bending, simplifying the process of component replacement.

Key features of the Board Saver include a top layer that matches the CQ172 footprint, via holes along the outer perimeter for soldering, and a central square hole that allows the FPGA to sit below the board level. The Board Saver is constructed from a 63-mil thick board, with no pads on the bottom, and is designed to be soldered from the outside edge of the exposed via holes to the flight board. This configuration ensures that the solder joints are visible and inspectable, facilitating easy removal when necessary.

The document emphasizes the importance of this technology in the context of aerospace applications, where reliability and the ability to iterate designs are critical. By providing a means to securely attach and detach FPGAs without damaging the underlying flight board, the Board Saver enhances the flexibility of FPGA development and testing.

For further inquiries or detailed information, the document provides contact details for JPL's Innovative Technology Assets Management team, encouraging collaboration and exploration of this technology's broader applications. Overall, the Board Saver represents a significant advancement in the field of aerospace electronics, enabling more efficient design processes while preserving the integrity of essential hardware.