A dynamic random-access memory (DRAM) circuit that tolerates single-event upsets (SEUs) has been developed. A single-event upset is a bit flip caused by ionizing radiation. In a DRAM, the state of each bit (0 or 1) is stored as charge on a buried capacitor. The impingement of an energetic charged particle can change the charge, and thus the state of the bit. There is no way to make a DRAM completely immune to SEUs, but the probability of a bit error in the DRAM output can be reduced significantly by use of redundancy; this is the concept on which the present SEU-tolerant design is based.
For protective redundancy, the DRAM incorporates three memory cells for each single cell that would otherwise be used. During recording, a bit is written in all three cells of a triple at the same time. Upon readout, the bit from the first cell is compared with that from the second cell; if the bits from the first and second cells are equal, then one of these bits is passed on to the data processor that requested the readout. If the bits from the first and second cells are not equal (because one was changed in an SEU), then the bit from the third cell is sent to the processor.
The comparison and selection of bits to pass on to the processor are accomplished by use of comparators and bus buffers. The SEU-tolerant DRAM also contains additional signal lines for full testing and for isolation and correction of faults.
This work was done by Steven Cole of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Electronics & Computers category. NPO-20474
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DRAM circuit tolerates single-event upsets
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Overview
The document discusses a novel dynamic random-access memory (DRAM) circuit developed by Steven Cole at NASA's Jet Propulsion Laboratory (JPL) that is designed to tolerate single-event upsets (SEUs) caused by ionizing radiation. SEUs can lead to bit flips in memory, which pose significant reliability challenges for dynamic memory systems, especially in aerospace applications where exposure to radiation is common.
In traditional DRAM, each bit is stored as charge on a buried capacitor, making it vulnerable to changes in state when impacted by energetic charged particles. The new SEU-tolerant DRAM design addresses this issue by implementing a redundancy strategy. Instead of using a single memory cell for each bit, the design incorporates three memory cells that store the same bit simultaneously. During data writing, the same value is recorded in all three cells. When data is read, the first two cells are compared. If they match, one of these bits is sent to the processor. If they differ—indicating that one cell has been affected by an SEU—the bit from the third cell is used, effectively ensuring data integrity through a majority vote mechanism.
The document highlights the technical aspects of the design, including the use of comparators and bus buffers to facilitate the comparison and selection of bits. Additionally, the SEU-tolerant DRAM includes extra signal lines for comprehensive testing, fault isolation, and correction, enhancing its reliability further.
The work is positioned as a significant improvement over previous DRAM technologies, which struggled to provide the necessary radiation hardness for flight systems. By utilizing this innovative approach, the new DRAM circuit offers a denser storage solution while maintaining a high level of reliability, making it suitable for critical applications in space exploration and other environments where radiation exposure is a concern.
Overall, this advancement represents a crucial step in enhancing the performance and reliability of memory systems used in aerospace technology, ensuring that data remains accurate and intact even in challenging conditions. The document serves as a technical disclosure of this innovative work, emphasizing its potential impact on future space missions and related technologies.
