A paper discusses NEXUS, a common, next-generation avionics interconnect that is transparently compatible with wired, fiber-optic, and RF physical layers; provides a flexible, scalable, packet switched topology; is fault-tolerant with submicrosecond detection/recovery latency; has scalable bandwidth from 1 Kbps to 10 Gbps; has guaranteed real-time determinism with sub-microsecond latency/jitter; has built-in testability; features low power consumption (< 100 mW per Gbps); is lightweight with about a 5,000-logic-gate footprint; and is implemented in a small Bus Interface Unit (BIU) with reconfigurable back-end providing interface to legacy subsystems.
NEXUS enhances a commercial interconnect standard, Serial RapidIO, to meet avionics interconnect requirements without breaking the standard. This unified interconnect technology can be used to meet performance, power, size, and reliability requirements of all ranges of equipment, sensors, and actuators at chip-to-chip, board-to-board, or box-to-box boundary.
Early results from in-house modeling activity of Serial RapidIO using VisualSim indicate that the use of a switched, high-performance avionics network will provide a quantum leap in spacecraft onboard science and autonomy capability for science and exploration missions.
This work was done by Yutao He, Eddy Shalom, Savio N. Chau, Raphael R. Some, and Gary S. Bolotin of Caltech for NASA’s Jet Propulsion Laboratory. NPO-47653
This Brief includes a Technical Support Package (TSP).
NEXUS Scalable and Distributed Next- Generation Avionics Bus for Space Missions
(reference NPO-47653) is currently available for download from the TSP library.
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Overview
The document presents an overview of NEXUS, a next-generation avionics interconnect developed by the California Institute of Technology and Jet Propulsion Laboratory (JPL) as part of a research task funded by JPL's R&TD program. The primary objective of NEXUS is to create a unified, highly capable interconnect system that meets the evolving demands of space missions.
NEXUS is designed to be compatible with various physical layers, including wired, fiber-optic, and RF technologies. It boasts several key features, such as scalable fault tolerance with sub-microsecond detection and recovery latency, bandwidth scalability ranging from 1 Kbps to 10 Gbps, and guaranteed real-time determinism with minimal latency and jitter. Additionally, NEXUS aims to achieve a significant reduction in wire mass (20% - 50%) and maintain low power consumption (less than 100mW per Gbps), all while keeping a lightweight footprint of fewer than 5000 logic gates.
The document emphasizes the importance of NEXUS in addressing the performance, power, size, and reliability requirements of a wide range of equipment, sensors, and actuators across various boundaries, including chip-to-chip, board-to-board, and box-to-box connections. Its modular and configurable design adheres to a common interconnect standard, allowing for adaptability in different applications.
The motivations behind the development of NEXUS are rooted in the need for advanced avionics systems that can support the increasing complexity and demands of future NASA and JPL missions. By providing a clear and feasible path-to-flight, NEXUS aims to ensure its integration into upcoming aerospace projects.
In summary, the document outlines the objectives, technology, and potential applications of the NEXUS interconnect, highlighting its role in enhancing the capabilities of avionics systems for space exploration. It serves as a technical support package under NASA's Commercial Technology Program, aiming to disseminate the results of aerospace-related developments with broader technological, scientific, and commercial implications. For further inquiries, the document provides contact information for the Innovative Technology Assets Management at JPL.
