Improved Starting Materials for Back-Illuminated Imagers

NASA’s Jet Propulsion Laboratory, Pasadena, California

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials.

Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes:

• A device layer on the front side, typically between 2 and 20 μm thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron);
• A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 μm thick; and
• A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 μm thick.

After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

For reasons too complex to discuss within the space available for this article, one modification that is necessary for reducing dark current and increasing quantum efficiency is the incorporation of a thin, heavily doped (e.g., p⁺⁺-doped with boron) silicon layer between the lightly doped device layer and the BOX layer. In prior research, an attempt to incorporate a thin, heavily doped layer by implanting boron at the BOX/device-silicon interface before bonding the BOX layer to the handle wafer did not yield the desired doping profile: The bonding process unavoidably included a high-temperature anneal that caused the implanted boron to diffuse away from the interface, thereby causing an undesired decrease in the doping concentration at the interface and an undesired increase in the doping concentration in the device layer. This concludes the background information.

A starting material of the present improved type, depicted in the middle and lower parts of figure, differs from prior SOI starting materials in the following ways:

• The front silicon layer is heavily doped [e.g., p⁺⁺-doped with boron], typically at a concentration of 10¹⁹ atoms/cm³ instead of being lightly doped at the conventional device concentration of 10¹⁵ atoms/cm³.
• There is a layer of thermal oxide between the front silicon layer and the BOX layer.
• The starting material is further preprocessed by growing, to an appropriate thickness, a front epitaxial silicon layer that is lightly doped (e.g., p-doped) typically at a concentration of 7 × 10¹⁴ boron atoms/cm³. This front epitaxial layer serves as the device layer in subsequent fabrication of an imager.

The advantage afforded by such an improved starting material arises from the fact that epitaxial silicon is grown at a temperature much lower than that of the anneal in the aforementioned BOX-to-handle-wafer-bonding process. Therefore, diffusion of boron away from the interface and into the device silicon is prevented. Optionally, one could perform an anneal at an intermediate temperature chosen to effect a small amount of diffusion to optimize the doping profile. Furthermore, the performance of the imager circuitry can be improved because the quality of the epitaxial silicon in the improved starting material is better than that of the float-zone device-layer silicon in prior SOI starting materials. All of the arguments made above would remain valid for cases in which electron-donor (n) dopants were substituted for p dopants.

This work was done by Bedabrata Pain of Caltech for NASA’s Jet Propulsion Laboratory. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management JPL Mail Stop 202-233
4800 Oak Grove Drive Pasadena, CA 91109-8099 (818) 354-2240 E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

Refer to NPO-41233, volume and number of this NASA Tech Briefs issue, and the page number.

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Topics:
Electrical systems Electronics & Computers Fabrication Imaging Manufacturing processes Research and development Starters and starting

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