A custom laboratory electronic timer circuit measures the durations of successive cycles of nominally highly stable input clock signals in as many as eight channels, for the purpose of statistically quantifying the small instabilities of these signals. The measurement data generated by this timer are sent to a personal computer running software that integrates the measurements to form a phase residual for each channel and uses the phase residuals to compute Allan variances for each channel. (The Allan variance is a standard statistical measure of instability of a clock signal.) Like other laboratory clock-cycle-measuring circuits, this timer utilizes an externally generated reference clock signal having a known frequency (100 MHz) much higher than the frequencies of the input clock signals (between 100 and 120 Hz). It counts the number of reference- clock cycles that occur between successive rising edges of each input clock signal of interest, thereby affording a measurement of the input clocksignal period to within the duration (10 ns) of one reference clock cycle. Unlike typical prior laboratory clockcycle- measuring circuits, this timer does not skip some cycles of the input clock signals. The non-cycle-skipping feature is an important advantage because in applications that involve integration of measurements over long times for characterizing nominally highly stable clock signals, skipping cycles can degrade accuracy.
The timer includes a field-programmable gate array that functions as a 20-bit counter running at the reference clock rate of 100 MHz. The timer also includes eight 20-bit latching circuits — one for each channel — at the output terminals of the counter. Each transition of an input signal from low to high causes the corresponding latching circuit to latch the count at that instant. Each such transition also sets a status flip-flop circuit to indicate the presence of the latched count. A microcontroller reads the values of all eight status flip flops and then reads the latched count for each channel for which the flip-flop indicates the presence of a count. Reading the count for each channel automatically causes the flipflop of that channel to be reset. The microcontroller places the counts in time order, identifies the channel number for each count, and transmits these data to the personal computer.
This work was done by Steven Cole of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/ Computers category.
The software used in this innovation is available for commercial licensing. Please contact Don Hart of the California Institute of Technology at (818) 393-3425. Refer to NPO-40233.
This Brief includes a Technical Support Package (TSP).
Eight-Channel Continuous Timer
(reference NPO-40233) is currently available for download from the TSP library.
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Overview
The document is a Technical Support Package for the Eight-Channel Continuous Timer Card, designated NPO-40233, developed by Steven W. Cole at the Measurement Technology Center. It is part of NASA's Commercial Technology Program, aimed at disseminating aerospace-related technological advancements with broader applications.
The Continuous Timer Card is designed to perform precise period and frequency measurements, addressing the limitations of older measurement systems, particularly those that relied on ISA slots, which are now obsolete in modern computers. The card features an 8-channel design, allowing it to measure signals with a nominal input frequency range of 100Hz to 120Hz. It operates using a 100MHz external reference clock, ensuring high accuracy in timing measurements.
The document outlines the general specifications of the card, including its power requirements, which consist of +5V for the microcontroller and +8V to +20V for the FPGA, both of which require less than 100mA of current. The card is equipped with an RS-232 interface for communication with PC-class computers, enabling the PC to control the activation of measurement channels during the measurement period. Importantly, the design ensures that no measurement periods are lost, and the output is provided in time sequence order.
The theory of operation section describes the card's 20-bit counter, which operates at 100MHz and utilizes gray code to minimize system noise. This counter can represent 1,048,576 unique states, with bits organized into two 8-bit bytes and one 4-bit nibble. The use of gray code allows only one bit to change state at each clock cycle, significantly reducing the number of bits changing simultaneously from 20 to just 3, thereby enhancing measurement stability.
Overall, the document serves as a comprehensive guide for understanding the Continuous Timer Card's functionality, specifications, and operational principles. It also provides information on how to access further assistance and resources related to NASA's research and technology initiatives. This package is a valuable resource for those interested in advanced measurement technologies and their applications in various fields.
