A method of fabricating channels having widths of tens of nanometers in silicon substrates and burying the channels under overlying layers of dielectric materials has been demonstrated. With further refinement, the method might be useful for fabricating nanochannels for manipulation and analysis of large biomolecules at single-molecule resolution. Unlike in prior methods, burying the channels does not involve bonding of flat wafers to the silicon substrates to cover exposed channels in the substrates. Instead, the formation and burying of the channels are accomplished in a more sophisticated process that is less vulnerable to defects in the substrates and less likely to result in clogging of, or leakage from, the channels.

This Scanning Electron Micrograph shows a cross section of a 20-by-80-nm channel formed between a silicon substrate and an overlying layer of dielectric material.

In this method, the first step is to establish the channel pattern by forming an array of sacrificial metal nanowires on an SiO2-on-Si substrate. In particular, the wire pattern is made by use of focused-ion-beam (FIB) lithography and a subsequent metallization/ lift-off process. The pattern of metal nanowires is then transferred onto the SiO2 layer by reactive-ion etching, which yields sacrificial SiO2 nanowires covered by metal. After removal of the metal covering the SiO2 nanowires, what remains are SiO2 nanowires on an Si substrate.

Plasma-enhanced chemical vapor deposition (PECVD) is used to form a layer of a dielectric material over the Si substrate and over the SiO2 wires on the surface of the substrate. FIB milling is then performed to form trenches at both ends of each SiO2 wire. The trenches serve as openings for the entry of chemicals that etch SiO2 much faster than they etch Si. Provided that the nanowires are not so long that the diffusion of the etching chemicals is blocked, the sacrificial SiO2 nanowires become etched out from between the dielectric material and the Si substrate, leaving buried channels. At the time of reporting the information for this article, channels 3 μm long, 20 nm deep, and 80 nm wide (see figure) had been fabricated by this method.

This work was done by Daniel Choi and Eui-Hyeok-Yang of Caltech for NASA's Jet Propulsion Laboratory. For more information, download the Technical Support Package (free white paper) at www.techbriefs.com/tsp under the Manufacturing & Prototyping category. In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
JPL
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

Refer to NPO-30839, volume and number of this NASA Tech Briefs issue, and the page number.



This Brief includes a Technical Support Package (TSP).
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Fabrication of Buried Nanochannels From Nanowire Patterns

(reference NPO-30839) is currently available for download from the TSP library.

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NASA Tech Briefs Magazine

This article first appeared in the July, 2007 issue of NASA Tech Briefs Magazine (Vol. 31 No. 7).

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Overview

The document is a Technical Support Package from NASA's Jet Propulsion Laboratory detailing advancements in the fabrication of buried nanochannels from nanowire patterns. It outlines a novel technique for creating longitudinal nanometer-scale embedded channels using a sacrificial nanowire etching method. This process begins with the fabrication of an array of nanometer-scale metal nanowire patterns on a silicon dioxide (SiO2) and silicon wafer using Focused Ion Beam (FIB) lithography, followed by a metalization and lift-off process.

The fabrication process involves several key steps: first, the metal nanowire patterns are transferred onto the SiO2 layer through reactive ion etching (RIE). After the removal of the metal mask patterns, nanometer-scale SiO2 nanowires are obtained, which serve as sacrificial patterns. Plasma Enhanced Chemical Vapor Deposition (PECVD) is then used to deposit dielectric materials over the nanowire patterns. FIB milling is employed to create trenches in both the front and rear regions of the nanowires, facilitating the etching process.

The document highlights the successful fabrication of longitudinal "embedded" nanochannels with dimensions of 20 nm x 80 nm, demonstrating the capability to create channels with a maximum length of 3 mm without encountering diffusion-blocking issues during the sacrificial etching process. This innovative approach offers significant advantages over prior methods, particularly in the precision and scalability of nanochannel fabrication.

The potential applications of this technology are extensive, including the manipulation and analysis of biomolecules such as DNA and proteins at single-molecule resolution, separation of biomolecules, development of biosensors, lab-on-a-chip systems, and miniature chemical factories. The technology is particularly relevant for NASA's fluidic systems and miniature chemical labs, which are also of interest to the Department of Defense for biological and chemical weapons detection.

In summary, this document presents a cutting-edge fabrication technique for nanochannels that could revolutionize various fields, including biotechnology and chemical analysis, while also providing substantial benefits for aerospace applications. The research reflects NASA's commitment to advancing technology with broader scientific and commercial implications.